1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more parcularly, to an improved structure for the retainer ring used on the polishing head of a chemical-mechanical polish (CMP) machine to retain a semiconductor wafer in position while performing the CMP process.
2. Description of Related Art
In semiconductor fabrications, the chemical-mechanical polish (CMP) technique is widely used for the global planarization of semiconductor wafers that are used for the fabrication of VLSI (very large-scale integration) and ULSI (ultra large-scale integration) integrated circuits.
FIGS. 1A and 1B are schematic diagrams showing a conventional CMP machine which includes a polishing table 10 on which a polishing pad 12 is layered, a polishing head 14 for holding a semiconductor wafer 16 in position, and a nozzle 18 for applying a mass of slurry to the semiconductor wafer 16 during the CMP process.
FIG. 1C shows a detailed inside structure of the polishing head 14. As shown, the polishing head 14 includes an air-pressure means 20 which can apply air pressure to a wafer loader 22 used to hold the wafer 16. In addition, a retainer ring 24 is mounted around the loader 22 and the wafer 16, which can retain the wafer 16 in fixed position during the CMP process. Moreover, a cushion pad (not shown) is placed between the wafer 16 and the loader 22.
FIGS. 2A-2B show a conventional structure for the retainer ring 24. Using the retainer ring structure of FIGS. 2A-2B, however, the slurry being spread therethrough into the polishing head 14 would be nonuniformly distributed over the surface of the wafer, thus causing the drawbacks of a large wafer-edge exclusion range, a low refuse removing rate, an inefficient use of the slurry, and a reduced life of use of the cushion pad. The resultant surface flatness of the wafer after undergoing a CMP process using the retainer ring of FIGS. 2A-2B is shown in FIG. 3. The graph of FIG. 3 shows the thickness of the wafer in relation to the various points of a straight line passing through the spinning center of the wafer. From the plot shown in FIG. 3, it can be seen that the flatness is not quite satisfactory. The standard deviation of the thickness data is about 5.06%.